This invention generally relates to digital data processing systems. More specifically it relates the interconnection of various units in such a system and the transfer of data among those units.
A digital data processing system comprises three basic elements: namely, a memory element, an input-output element and a processor element. The memory element stores information in addressable storage locations. This information includes data and instructions for processing the data. The processor element transfers information to and from the memory element and interprets the incoming information as either data or instructions. The input-output elements also communicate with the memory element in order to provide some means for providing useful information to the digital data processing system and to obtain useful information from it.
Over the years many different types of digital data processing systems have been developed. However, this development has been directed toward evolving new processor elements with more efficient architecture, larger and faster memory elements and more sophisticated input-output elements. There has been little change in the technology involved in transferring information among the various elements in the data processing system. In fact, all the data processing systems of which we are aware can be classified by the timing method that they use. There are only two timing categories: synchronous and asynchronous timing.
Digital data processing systems that utilize synchronous timing usually include a master clock that controls all operations in all elements. This master clock generates timing signals that control operations in the processor element and also in the memory and input-output elements that connect to an interconnecting bus. As all the elements in the system are synchronized to the master clock, the master clock frequency must be set to operate in a way that is compatible with the slowest element in the system. The transfer rates between elements impose ultimate limitations on the speeds with which the faster elements can operate. Thus a slow transfer rate slows the entire system so that the system runs below the theoretical efficiency of many of its component units.
Other digital data processing systems utilize asynchronous timing over their interconnections. With asynchronous timing each element is free to operate at its most efficient rate. Typically two elements communicate with each other when one element initiates a data transfer over an interconnecting bus. Then the one element controls the bus to the exclusion of all third elements in the system until the other element acknowledges that the requested transfer has been completed. Systems using asynchronous timing tend to be somewhat faster than their counterpart synchronous systems because they can make some transfers at a greater rate than the slowest element in the system, while maintaining the ability to communcicate more slowly with the slower elements. However, asynchronous transfers do have drawbacks in some applications. In some asynchronous systems, once a transfer operation has been initiated, the entire bus is unavailable to any elements other than the two involved in the transfer until that transfer is completed. Thus transfers involving slower elements hold up operation of the faster elements and reduce their efficiencies below their theoretical levels.
Despite the drawbacks of both synchronous and asynchronous transfers, most digital data processing systems still are built solely around either one or the other, but not both timing schemes. The selection of one over the other apparently depends upon the predicted applications for the digital data processing system. Thus, in some applications unacceptable operating speeds may be encountered while in others the speeds are acceptable.
There is described in copending U.S. patent application Ser. No. 845,415 filed Oct. 25, 1977, and now abandoned, a digital data processing system in which a synchronous bus interconnects the individual elements. Unlike prior systems, however, this system does not extend the timing control exerted on the bus throughout all the elements. Each element operates at its own maximum speed while it is not connected to the bus. At the time that element is to make a transfer, it prepares to make a transfer in synchronism with the bus. While this system greatly increases the overall speed of communications, by itself this does not increase the overall transfer rate to the maximum potential rate.
One potential problem that can arise in such a system as described in that U.S. patent application is overloading of a specific element in the system with transfers. The memory element, for example, is very susceptible to overloadinge. The vast majority of transfers involve this element. Nearly all exchanges involving the processor element involve it. In large systems that utilize secondary storage facilities, such as tape and disk memories, most exchanges of information involving those facilities are made with the memory element. Various approaches have been taken to reduce the load on the memory element including the use of plural elements in an interleaved arrangement and the use of overlapping memory cycles. In recent years the response times for the memory elements also have been reduced greatly. However, the response times are still slower than the normal transfer rates that are encountered in a relatively complex data system, so overloads persist. In some systems the ability of the memory element to respond to requests for information exchanges can become the limiting factor on the overall operating characteristics of the entire system. Moreover, such overloading can lead to errors, so oftentimes the memory contains circuitry for signalling an overload condition that halts further operation of the system. Alternatively, other elements must be constructed to sense the inability of the memory element to respond and then try to effect the exchange at a later time. Providing for these conditions obviously increases the complexity and costs of the other elements that exchange information with the memory element.
Therefore, it is an object of this invention to provide a memory element for a data processing system in which the elements are enabled to exchange information at very fast rates.
Another object of this invention is to provide a memory element for use in a data processing system in which the memory element is capable of processing multiple requests for exchanges of information.
Still another object of this invention is to provide a memory element for a data processing system in which the memory element is enabled to respond to substantially simultaneous requests for information exchanges from different elements in the system without becoming overloaded.